1. Field of the Invention
This invention relates to ferroelectric field effect transistors, and more particularly to ferroelectric nondestructive read-out memories utilizing such transistors and methods of fabricating such transistors and memories.
2. Statement of the Problem
It has been known since at least the 1950's that if a practical ferroelectric memory could be made, it would provide a fast, dense, non-volatile memory that could be operated at relatively low voltages. See Orlando Auciello et al., "The Physics of Ferroelectric Memories", Physics Today, July 1998, pp. 22-27. The principal type of ferroelectric memory being explored today is the non-volatile ferroelectric random access memory or NVFRAM. Ibid. A disadvantage of the NVFRAM is that, in the process of reading it, the information it holds is destroyed and, therefore, the read function must be followed by a rewrite function. Destructive reading followed by rewriting generally requires operating a memory with two transistors and two capacitors ("2T-2C"), which reduces overall circuit density and efficiency, as well as increase manufacturing costs.
It has been postulated for at least 40 years, however, that it may be possible to design a nonvolatile, nondestructive read-out ("NDRO") memory in which the memory element is a single ferroelectric field effect transistor ("FET"), thereby reducing at least some of the complexity of conventional 2T-2C operation. See Shu-Yau Wu, "A New Ferroelectric Memory Device, Metal-Ferroelectric-Semiconductor Transistor", in IEEE Transactions On Electron Devices, pp. 499-504, August 1974; S. Y. Wu, "Memory Retention and Switching Behavior Of Metal-Ferroelectric-Semiconductor Transistors", in Ferroelectrics, Vol. 11, pp. 379-383, 1976; and J. R. Scott, C. A. Paz De Araujo, and L. D. McMillan, "Integrated Ferroelectrics", in Condensed Matter News, Vol. 1, No. 3, pp. 15-20, 1992. Because the ferroelectric memory effect measured in the early devices of Wu was only a temporary single state effect rather than a long-lived two state effect, it is now believed that this effect was a charge injection effect rather than an effect due to ferroelectric switching.
A structure well-known in the art is the so-called metal-ferroelectric-semiconductor FET ("MFS-FET"), in which typically a ferroelectric oxide is formed on the semiconductor substrate, and the metal gate electrode is located on the ferroelectric oxide. When a ferroelectric oxide thin film, such as PZT, is formed directly on a semiconductor substrate, such as silicon, high leakage current, low retention times and fatigue are common problems. It is commonly believed in the art that some of this is a result of a poor interface between ferroelectric oxides and silicon. The poor interface may be a result of incompatibility of crystalline ferroelectric oxides with the crystal lattices and thermal coefficients of silicon.
Also, when a thin film of ferroelectric oxide is in direct electrical connection with the gate oxide layer of the transistor gate, it is difficult to apply sufficient voltage to the ferroelectric thin film to switch its polarization. A ferroelectric thin film and a gate oxide may be viewed as two capacitors in series. The dielectric constant of the ferroelectric thin film (usually 100-1000) is much higher than the dielectric constant of typical gate oxides (usually about 3-5). As a result, most of the voltage drop occurs across the low dielectric constant material, and an extra high operational voltage is required to switch the polarization of the ferroelectric thin film. This can lead to electrical breakdown of the gate oxide and other materials in the circuit. Further, a high operational voltage in excess of 3-5 volts would render the device incompatible with conventional integrated circuit art.
To reduce interface problems, structures have been designed in which an insulating oxide layer, such as CeO.sub.2 or Y.sub.2 O.sub.3, is deposited by sputtering or electron-beam evaporation on the semiconductor substrate before depositing the ferroelectric layer and gate electrode. Such a structure is referred to in the art as a metal-ferroelectric-insulator-semiconductor FET ("MFIS-FET"). Recently, a MFIS-FET device has been reported that appears to show true ferroelectric memory behavior. See Tadahiko Hirai et al., "Formation of Metal/Ferroelectric/Insulator/Semiconductor Structure With A CeO.sub.2 Buffer Layer", in Japanese Journal of Applied Physics, Vol. 33, Part I, No. 9B, pp. 5219-5222, September 1994; Tadahiko Hirai et al., "Characterization of Metal/Ferroelectric/Insulator/Semiconductor Structure With A CeO.sub.2 Buffer Layer", in Japanese Journal of Applied Physics, Vol. 34, Part I, No. 8A, pp. 4163-4166, August 1995; Tadahiko Hirai et al., "Crystal and Electrical Characterizations of Epitaxial Ce.sub.x Zr.sub.1-x O.sub.2 Buffer Layer for the Metal/Ferroelectric/Insulator/Semiconductor Field Effect Transistor", in Japanese Journal of Applied Physics, Vol. 35, Part I, No. 9A, pp. 5150-5153, September 1996; Yong Tae Kim et al., "Memory Window of Pt/SrBi.sub.2 Ta.sub.2 O.sub.9 /CeO.sub.2 /SiO.sub.2 /Si Structure For Metal Ferroelectric Insulator Semiconductor Field Effect Transistor", Applied Physics Letters, Vol. 71 No. 24, Dec. 15, 1997, pp. 3507-3509; Dong Suk Shin et al., "A Proposal of Pt/SrBi.sub.2 Ta.sub.2 O.sub.9 /CeO.sub.2 /Si Structure for Non Destructive Read Out Memory Devices", Extended Abstracts of 1997 Int'l Conference on Solid State Devices and Materials, p. 32; and U.S. Pat. No. 5,744,374, issued Apr. 28, 1998 to Jong Moon. It is believed that an insulator layer located on the silicon substrate between the substrate and the ferroelectric thin film avoids the problems caused by a ferroelectric-semiconductor interface.
The interface insulator layer of the prior art has been deposited using target-sputtering methods or electron-beam evaporation. Such methods are generally complex, and they do not provide flexibility and accurate control of chemical composition when depositing interface insulator layers.
EMOD processes are known for forming ferroelectric materials and ABO.sub.3 type metal oxides. See, U.S. Pat. No. 5,514,822 issued May 7, 1996 to Scott et al. However, the EMOD processes described in the prior art require high annealing temperatures, and it was believed that these temperatures would give rise to significant thicknesses of oxides, that is, on the order of 100 nm, particularly of semiconductor oxides, that would lead to charge injection and the other problems discussed above. Moreover, the required extreme thinness of the films required for the interface insulator to be effective, i.e. 5 nanometers (nm) to 50 nm, had not previously been obtainable with EMOD processes. Because of these problems, and other unusual surface phenomena and operating conditions encountered in processes using EMOD solutions, it was previously believed that EMOD processes could not be utilized to form a metal oxide interface insulator layer in a ferroelectric FET memory device between the ferroelectric thin film and the semiconductor substrate.